See there! A son is born — and we pronounce him fit to fight.
There are blackheads on his shoulders, and he pees himself in the night.
We’ll make a man of him put him to trade
teach him to play Monopoly and to sing in the rain.
The lyrics above are from Ian Anderson’s “Thick as a brick”. A bit sarcastic, I agree, but they somehow felt fit for what is going to follow in this blog. See there, a(nother) Open FXx circuit is born! After Open USB FXS has gotten itself into a relatively mature state, I thought, what the heck, why not give that poor FXS circuit a little brother to keep it company? And thus came Open USB FXO.
What is Open USB FXO — or, more correctly, what will it be when it grows up enough to see itself becoming a real circuit? The answer is “a Foreign eXchange Office” adapter, able to connect your computer to the PTT plug on the wall. Forgot to say, your computer will have to run Linux and Asterisk.
I decided to start with an Open USB FXO circuit design by the end of 2010. Other tasks kept me away from posting any details about it until March 2011. Soon I came up with the following schematic (warning! it’s not ready and it’s not going to work!):
Cannot make out anything on the picture above? Try clicking on it and you will get a zoomed-in version that’s readable (though if you cannot make out the big, red warning, you may need eyeglasses — I ‘ll come back to that warning in a second).
Wow, might you think, this schematic is already too advanced! How did that guy come up with it? Well, let me help you change your mind. Much like Open USB FXS, the schematic above is little more than a port of the manufacturer’s reference application circuit. Engineering starts from selecting the telephony chipset, in this case Silicon Labs’ Si3050, together with the line driver chip, Si3019. From then on, what I did as a designer was just to take a look at the manufacturer’s data sheet, import that into CadSoft Eagle and add the same PIC-based front-end that I already had from Open USB FXS — voilà, here came Open USB FXO!
And then it took less than ten minutes to figure out that this was all wrong.
How come? Well, I overlooked a slight detail: contrarily to the Si3210 in my Open USB FXS design, the Si3050 operates at 3.3V. The PIC 18F2550 operates at 5V. They do not interface, full stop. So much for my wonderful first-try design.
Thus, there were two things that I could do: use a 5V/3.3V level converter chip to interface between the 18F2550 and the 3050, or use a different microcontroller that operates at 3.3V. I quickly dropped the first alternative, because it would make the circuit too complicated and add to its cost. Starting with the second alternative, I had already invested much into learning the architecture, the instruction set, the USB idiosyncracies, and the inners of the PIC 18F2550 to let all that go. So, I looked for a different PIC that would be as much as possible compatible with the 18F2550 but operate at 3.3V. That did not take too long to spot: it was the 18F25J50.
At first, the two chips looked pin-compatible, and thus I thought that I could just replace the 18F25J50 in the schematic. Halas, I was once more wrong. There are quite a few differences between the two chips:
The 18F25J50 has about one zillion new special-function registers that do not exist in the 15F2550 (but OK, if I did not need these, I did not have to learn about them all, did I?).
The clock modes are different. However, the 18F25J50 datasheet lists a 20MHz/divide-by-5 option that is compatible with that of the 18F2550 (needless to say: I ‘d have to stick with 48 MHz core clocking if I wanted to re-use my TMR1 data-handling routine from Open USB FXS).
ICSP programming is different. The 18F25J50 does not have a VPP pin, and uses \MCLR instead (\ stands for “not”: the pin has inverted logic). But then, \MCLR cannot be connected directly to VDD as in my former design, and needs a typical 1k-10k pull-up.
The actual core of the 18F25J50 runs at an even lower voltage, 2.5 V. Of course, the chip has an internal regulator that supplies this voltage. To use that regulator, an external pin (pin 6, called VDDCORE in 18F25J50, which has taken the place of 18F2550’s RA4, which, in turn, has vanished in 18F25J50) needs to be connected via a capacitor to VSS.
The 18F25J50 does not have an EEPROM (puff! — there goes the nice code I developed for storing a board ID and the auto-bootloader…or maybe not? Michrochip have a promising Application Note on their site called “Emulating Data EEPROM for PIC18 and PIC24 Microcontrollers” on their site).
I am not sure whether the bootloader software that I have been using for the 15F2550 will work on the 15F25J50. Maybe it will need modifications. But there is a nice Application Note on that as well.
And then, of course, I would need to adjust VDD from the USB-supplied 5V to 3.3V. A couple of 1N4148 diodes in series would do that alright, yielding about 3.6-3.4 V depending on the actual diode make and the current drawn.
(update, Apr 10): And it seems that the list doesn’t end here; the SDI and SCK pins are also in different places… I am checking for more diffs, while creating the Eagle library for the 25J50. (Update, Apr 12): However, the 25J50 has software-programmable I/O pins, among which are the SPI2 pins (SDI2, SDO2, SCK2). I might program these to coincide with the pins of the 2550’s SPI, and thus save me the additional changes in the schematic. Perfect!
So here is where I stand right now. I am studying the data sheet and the Application Notes to see if I can use the PIC18F25J50. I think in the end I ‘ll manage it, but who knows… Giving birth is not an easy thing, it seems. Especially if the parent is a guy like me, who first puts down a design and then consults the data sheets. Nevertheless, let us be optimistic. It’s a newborn circuit after all, so let us show it –and its parent– some forgiveness for all the small and big mistakes it contains in its design, and hope that they will get eventually all fixed. Hey, welcome to life, Open USB FXO!